2008-08-0806:48+0000dzhimievfpga/x359_experimentaldescrproc353.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/descrproc353.v?revision=1.3&view=markupMExp4743fpga/x359_experimentalmcontr359.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/mcontr359.v?revision=1.3&view=markupMExp00fpga/x359_experimentalx359.bit1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/x359.bit?revision=1.3&view=markupMExp445563fpga/x359_experimentalx359.tf1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/x359.tf?revision=1.3&view=markupMExp1212fpga/x359_experimentalx359.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/x359.v?revision=1.3&view=markupMExp136152fpga/x359_experimentalx359_sim.sh1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/x359_sim.sh?revision=1.3&view=markupMExp12ch0 write -> ch2 read -> ch1 write -> ch4 read2008-08-0115:44+0000dzhimievfpga/x359_experimentalclkios353.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/clkios353.v?revision=1.2&view=markupMExp00fpga/x359_experimentaldescrproc353.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/descrproc353.v?revision=1.2&view=markupMExp5449fpga/x359_experimentaldwt_1d.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/dwt_1d.v?revision=1.1&view=markupAExp00fpga/x359_experimentalglbl.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/glbl.v?revision=1.2&view=markupMExp00fpga/x359_experimentalgradient.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/gradient.v?revision=1.1&view=markupAExp00fpga/x359_experimentali2csbr.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/i2csbr.v?revision=1.2&view=markupMExp00fpga/x359_experimentalmacros353.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/macros353.v?revision=1.2&view=markupMExp00fpga/x359_experimentalmcontr359.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/mcontr359.v?revision=1.2&view=markupMExp298171fpga/x359_experimentalsdram_phase.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/sdram_phase.v?revision=1.2&view=markupMExp00fpga/x359_experimentalsdseq353.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/sdseq353.v?revision=1.2&view=markupMExp434fpga/x359_experimentalx359.bit1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/x359.bit?revision=1.2&view=markupMExp562390fpga/x359_experimentalx359.tf1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/x359.tf?revision=1.2&view=markupMExp35184fpga/x359_experimentalx359.ucf1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/x359.ucf?revision=1.2&view=markupMExp66fpga/x359_experimentalx359.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/x359.v?revision=1.2&view=markupMExp1004634fpga/x359_experimentalx359_sim.sh1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/x359_sim.sh?revision=1.2&view=markupMExp20not stable, horizontal transform only2008-08-0115:41+0000dzhimievfpga/x359_experimental/test_scriptsmem_read.php1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/mem_read.php?revision=1.3&view=markupMExp00fpga/x359_experimental/test_scriptsmem_test.php1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/mem_test.php?revision=1.3&view=markupMExp3818fpga/x359_experimental/test_scriptsphases_adjust.php1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/phases_adjust.php?revision=1.3&view=markupMExp11fpga/x359_experimental/test_scriptsreg_read.php1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/reg_read.php?revision=1.1&view=markupAExp00fpga/x359_experimental/test_scriptsreg_write.php1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/reg_write.php?revision=1.3&view=markupMExp00fpga/x359_experimental/test_scriptssensors_init.php1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/sensors_init.php?revision=1.3&view=markupMExp00fpga/x359_experimental/test_scriptsswitch_channel.php1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/switch_channel.php?revision=1.3&view=markupMExp2828fpga/x359_experimental/test_scriptstests_for_96mhz.php1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/tests_for_96mhz.php?revision=1.4&view=markupMExp60fpga/x359_experimental/test_scriptstrigger_mode_init.php1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/trigger_mode_init.php?revision=1.3&view=markupMExp00latest scripts for unstable version2008-06-1607:43+0000dzhimievfpga/x359_experimental/test_scriptsmem_read.php1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/mem_read.php?revision=1.2&view=markupMExp00fpga/x359_experimental/test_scriptsmem_test.php1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/mem_test.php?revision=1.2&view=markupMExp2138fpga/x359_experimental/test_scriptsphases_adjust.php1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/phases_adjust.php?revision=1.2&view=markupMExp11fpga/x359_experimental/test_scriptsreg_write.php1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/reg_write.php?revision=1.2&view=markupMExp00fpga/x359_experimental/test_scriptsswitch_channel.php1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/switch_channel.php?revision=1.2&view=markupMExp2828fpga/x359_experimental/test_scriptstests_for_96mhz.php1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/tests_for_96mhz.php?revision=1.3&view=markupMExp3830fpga/x359_experimental/test_scriptstrigger_mode_init.php1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/trigger_mode_init.php?revision=1.2&view=markupMExp00mcontr address range changed from 0x0820-0x082F to 0x0840-0x085F (for making extra channels)2008-06-1315:38+0000jlarreyfpga/theora_353/driverMakefile1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/Makefile?revision=1.1&view=markupAExp00fpga/theora_353/drivercc353.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/cc353.c?revision=1.1&view=markupAExp00fpga/theora_353/drivercc353.h1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/cc353.h?revision=1.1&view=markupAExp00fpga/theora_353/drivercc3x3.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/cc3x3.c?revision=1.1&view=markupAExp00fpga/theora_353/drivercc3x3.h1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/cc3x3.h?revision=1.1&view=markupAExp00fpga/theora_353/drivercci2c.h1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/cci2c.h?revision=1.1&view=markupAExp00fpga/theora_353/drivercircbuf.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/circbuf.c?revision=1.1&view=markupAExp00fpga/theora_353/drivercircbuf.h1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/circbuf.h?revision=1.1&view=markupAExp00fpga/theora_353/drivercxdma.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/cxdma.c?revision=1.1&view=markupAExp00fpga/theora_353/drivercxdma.h1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/cxdma.h?revision=1.1&view=markupAExp00fpga/theora_353/drivercxdma353.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/cxdma353.c?revision=1.1&view=markupAExp00fpga/theora_353/drivercxdma353.h1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/cxdma353.h?revision=1.1&view=markupAExp00fpga/theora_353/drivercxi2c.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/cxi2c.c?revision=1.1&view=markupAExp00fpga/theora_353/drivercxsdram.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/cxsdram.c?revision=1.1&view=markupAExp00fpga/theora_353/drivercxsdram.h1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/cxsdram.h?revision=1.1&view=markupAExp00fpga/theora_353/drivercxsdram353.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/cxsdram353.c?revision=1.1&view=markupAExp00fpga/theora_353/driverexif.h1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/exif.h?revision=1.1&view=markupAExp00fpga/theora_353/driverexif353.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/exif353.c?revision=1.1&view=markupAExp00fpga/theora_353/driverexif353.h1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/exif353.h?revision=1.1&view=markupAExp00fpga/theora_353/driverext353.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/ext353.c?revision=1.1&view=markupAExp00fpga/theora_353/driverfpga_common.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/fpga_common.c?revision=1.1&view=markupAExp00fpga/theora_353/driverfpga_io.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/fpga_io.c?revision=1.1&view=markupAExp00fpga/theora_353/driverfpga_io.h1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/fpga_io.h?revision=1.1&view=markupAExp00fpga/theora_353/driverfpga_sdram.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/fpga_sdram.c?revision=1.1&view=markupAExp00fpga/theora_353/driverfpga_sdram.h1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/fpga_sdram.h?revision=1.1&view=markupAExp00fpga/theora_353/driverfpga_sdram353.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/fpga_sdram353.c?revision=1.1&view=markupAExp00fpga/theora_353/driverfpgaclocks.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/fpgaclocks.c?revision=1.1&view=markupAExp00fpga/theora_353/driverfpgaclocks353.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/fpgaclocks353.c?revision=1.1&view=markupAExp00fpga/theora_353/driverfpgaconf333.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/fpgaconf333.c?revision=1.1&view=markupAExp00fpga/theora_353/driverfpgaconfi2c.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/fpgaconfi2c.c?revision=1.1&view=markupAExp00fpga/theora_353/driverfpgaconfi2c.h1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/fpgaconfi2c.h?revision=1.1&view=markupAExp00fpga/theora_353/driverfpgactrl.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/fpgactrl.c?revision=1.1&view=markupAExp00fpga/theora_353/driverfpgactrl.h1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/fpgactrl.h?revision=1.1&view=markupAExp00fpga/theora_353/driverfpgactrl353.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/fpgactrl353.c?revision=1.1&view=markupAExp00fpga/theora_353/driverfpgajtag.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/fpgajtag.c?revision=1.1&view=markupAExp00fpga/theora_353/driverfpgajtag353.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/fpgajtag353.c?revision=1.1&view=markupAExp00fpga/theora_353/driverhist.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/hist.c?revision=1.1&view=markupAExp00fpga/theora_353/driverhist.h1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/hist.h?revision=1.1&view=markupAExp00fpga/theora_353/driverhist353.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/hist353.c?revision=1.1&view=markupAExp00fpga/theora_353/drivermt9x001.c1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/mt9x001.c?revision=1.1&view=markupAExp00fpga/theora_353/drivermt9x001.h1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/mt9x001.h?revision=1.1&view=markupAExp00fpga/theora_353/driverx353.h1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/x353.h?revision=1.1&view=markupAExp00fpga/theora_353/driverx353t.h1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/x353t.h?revision=1.2&view=markupRdead00fpga/theora_353/driverx3x3.h1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/x3x3.h?revision=1.1&view=markupAExp00*** empty log message ***2008-06-1315:30+0000jlarreyfpga/theora_353bms.dat1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/bms.dat?revision=1.1&view=markupAExp00fpga/theora_353x353.ucf1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353.ucf?revision=1.3&view=markupAExp00fpga/theora_353/bitx353.bit1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/bit/x353.bit?revision=1.2&view=markupMExp17151444*** empty log message ***2008-06-1213:28+0000jlarreyfpga/theora_353__ISE_repository_x353t.ise_.lock1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/__ISE_repository_x353t.ise_.lock?revision=1.2&view=markupRdead00fpga/theora_353dc_predict.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/dc_predict.v?revision=1.2&view=markupMExp3934fpga/theora_353dma_fifo353.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/dma_fifo353.v?revision=1.2&view=markupRdead00fpga/theora_353encoderDCAC333.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/encoderDCAC333.v?revision=1.2&view=markupRdead00fpga/theora_353ioports353.v1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/ioports353.v?revision=1.4&view=markupMExp31fpga/theora_353mcontr_8chn.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/mcontr_8chn.v?revision=1.3&view=markupMExp104fpga/theora_353pxdpath.sav1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/pxdpath.sav?revision=1.2&view=markupRdead00fpga/theora_353reorder_hilbert.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/reorder_hilbert.v?revision=1.2&view=markupMExp11fpga/theora_353sdseq353.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/sdseq353.v?revision=1.2&view=markupRdead00fpga/theora_353sensor12bits.v1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/sensor12bits.v?revision=1.4&view=markupMExp33fpga/theora_353sensorpix353.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/sensorpix353.v?revision=1.3&view=markupMExp2610fpga/theora_353sensorpix353t.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/sensorpix353t.v?revision=1.3&view=markupRdead00fpga/theora_353x353.ucf1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353.ucf?revision=1.2&view=markupRdead00fpga/theora_353x353.v1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353.v?revision=1.4&view=markupMExp5619fpga/theora_353x353_1.tf1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353_1.tf?revision=1.2&view=markupRdead00fpga/theora_353x353_1.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353_1.v?revision=1.2&view=markupRdead00fpga/theora_353x353_1tasks.tf1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353_1tasks.tf?revision=1.2&view=markupRdead00fpga/theora_353x353_347_1.tf1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353_347_1.tf?revision=1.2&view=markupRdead00fpga/theora_353x353_347_sim.sh1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353_347_sim.sh?revision=1.2&view=markupRdead00fpga/theora_353x353_import.tcl1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353_import.tcl?revision=1.2&view=markupRdead00fpga/theora_353x353_sim.sh1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353_sim.sh?revision=1.3&view=markupMExp12fpga/theora_353x353_sta.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353_sta.v?revision=1.2&view=markupRdead00fpga/theora_353x353_summary.html1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353_summary.html?revision=1.2&view=markupRdead00fpga/theora_353x353t.ise1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353t.ise?revision=1.2&view=markupRdead00fpga/theora_353x353t.ise_ISE_Backup1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353t.ise_ISE_Backup?revision=1.2&view=markupRdead00fpga/theora_353x353t.restore1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353t.restore?revision=1.2&view=markupRdead00fpga/theora_353x353t.tf1.8http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353t.tf?revision=1.8&view=markupMExp6566fpga/theora_353x353t_tasks.tf1.5http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353t_tasks.tf?revision=1.5&view=markupMExp07Back with 353 interrupts, simulation seems to work2008-05-2309:10+0000jlarreyfpga/theora_353/bitx353.bit1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/bit/x353.bit?revision=1.1&view=markupAExp00Compiled configuration file (uses 333 interrupts manager)2008-05-2309:07+0000jlarreyfpga/theora_353/interrupts333interrupts333t.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/interrupts333/interrupts333t.v?revision=1.1&view=markupAExp00fpga/theora_353/interrupts333ioports353.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/interrupts333/ioports353.v?revision=1.1&view=markupAExp00fpga/theora_353/interrupts333x353.h1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/interrupts333/x353.h?revision=1.1&view=markupAExp00fpga/theora_353/interrupts333x353.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/interrupts333/x353.v?revision=1.1&view=markupAExp00fpga/theora_353/interrupts333x353_sim.sh1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/interrupts333/x353_sim.sh?revision=1.1&view=markupAExp00fpga/theora_353/interrupts333x353t.tf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/interrupts333/x353t.tf?revision=1.1&view=markupAExp00fpga/theora_353/interrupts333x353t_parameters.tf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/interrupts333/x353t_parameters.tf?revision=1.1&view=markupAExp00fpga/theora_353/interrupts333x353t_tasks.tf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/interrupts333/x353t_tasks.tf?revision=1.1&view=markupAExp00Use these files to manage interrupts like in the 333 (works in simulation)2008-05-2223:33+0000dzhimievfpga/x359_experimental/test_scriptstests_for_96mhz.php1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/tests_for_96mhz.php?revision=1.2&view=markupMExp44removed phase adjustments2008-05-2222:57+0000dzhimievfpga/x359_experimental/test_scriptsphases_adjust.php1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/phases_adjust.php?revision=1.1&view=markupAExp00fpga/x359_experimental/test_scriptsreg_write.php1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/reg_write.php?revision=1.1&view=markupAExp00fpga/x359_experimental/test_scriptssensors_init.php1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/sensors_init.php?revision=1.2&view=markupMExp30fpga/x359_experimental/test_scriptsswitch_channel.php1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/switch_channel.php?revision=1.1&view=markupAExp00fpga/x359_experimental/test_scriptsswitch_to_ch2.php1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/switch_to_ch2.php?revision=1.2&view=markupRdead30+ 0x0800 - current channel number register+ DCMs independent phase adjustmentuseful scripts2008-05-2208:21+0000jlarreyfpga/theora_353clkios353.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/clkios353.v?revision=1.2&view=markupMExp71fpga/theora_353sdram_phase.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/sdram_phase.v?revision=1.2&view=markupMExp22Fixed phase issues2008-05-0119:33+0000dzhimievfpga/x359_experimental/test_scriptsmem_read.php1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/mem_read.php?revision=1.1&view=markupAExp00fpga/x359_experimental/test_scriptsmem_test.php1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/mem_test.php?revision=1.1&view=markupAExp00fpga/x359_experimental/test_scriptssensors_init.php1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/sensors_init.php?revision=1.1&view=markupAExp00fpga/x359_experimental/test_scriptsswitch_to_ch2.php1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/switch_to_ch2.php?revision=1.1&view=markupAExp00fpga/x359_experimental/test_scriptstests_for_96mhz.php1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/tests_for_96mhz.php?revision=1.1&view=markupAExp00fpga/x359_experimental/test_scriptstrigger_mode_init.php1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/test_scripts/trigger_mode_init.php?revision=1.1&view=markupAExp00experiments2008-05-0119:32+0000dzhimievfpga/x359_experimentalclkios353.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/clkios353.v?revision=1.1&view=markupAExp00fpga/x359_experimentalddr.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/ddr.v?revision=1.1&view=markupAExp00fpga/x359_experimentalddr_parameters.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/ddr_parameters.v?revision=1.1&view=markupAExp00fpga/x359_experimentaldescrproc353.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/descrproc353.v?revision=1.1&view=markupAExp00fpga/x359_experimentalglbl.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/glbl.v?revision=1.1&view=markupAExp00fpga/x359_experimentali2csbr.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/i2csbr.v?revision=1.1&view=markupAExp00fpga/x359_experimentalioports353.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/ioports353.v?revision=1.1&view=markupAExp00fpga/x359_experimentalmacros353.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/macros353.v?revision=1.1&view=markupAExp00fpga/x359_experimentalmcontr359.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/mcontr359.v?revision=1.1&view=markupAExp00fpga/x359_experimentalsdram_phase.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/sdram_phase.v?revision=1.1&view=markupAExp00fpga/x359_experimentalsdseq353.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/sdseq353.v?revision=1.1&view=markupAExp00fpga/x359_experimentalsensor.dat1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/sensor.dat?revision=1.1&view=markupAExp00fpga/x359_experimentalsensor12bits.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/sensor12bits.v?revision=1.1&view=markupAExp00fpga/x359_experimentalx359.bit1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/x359.bit?revision=1.1&view=markupAExp00fpga/x359_experimentalx359.tf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/x359.tf?revision=1.1&view=markupAExp00fpga/x359_experimentalx359.ucf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/x359.ucf?revision=1.1&view=markupAExp00fpga/x359_experimentalx359.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/x359.v?revision=1.1&view=markupAExp00fpga/x359_experimentalx359_sim.sh1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x359_experimental/x359_sim.sh?revision=1.1&view=markupAExp00experiments2008-04-1713:22+0000jlarreyfpga/theora_353/driverx353t.h1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/driver/x353t.h?revision=1.1&view=markupAExp00New definitions for x353 theora. Some macros at the end (/*** A bunch of macros ***/ may be obsolete.2008-04-1010:16+0000jlarreyfpga/theora_353acdcscale.dat1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/acdcscale.dat?revision=1.1&view=markupAExp00fpga/theora_353defines333.vh1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/defines333.vh?revision=1.1&view=markupAExp00fpga/theora_353focus_filt.dat1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/focus_filt.dat?revision=1.1&view=markupAExp00fpga/theora_353huffman.dat1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/huffman.dat?revision=1.1&view=markupAExp00fpga/theora_353hufftab80.dat1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/hufftab80.dat?revision=1.1&view=markupAExp00fpga/theora_353linear256rgb.dat1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/linear256rgb.dat?revision=1.1&view=markupAExp00fpga/theora_353map.dat1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/map.dat?revision=1.1&view=markupAExp00fpga/theora_353quantization_100.dat1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/quantization_100.dat?revision=1.1&view=markupAExp00fpga/theora_353use_huffman_table.dat1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/use_huffman_table.dat?revision=1.1&view=markupAExp00Uploading missing files2008-04-0908:21+0000jlarreyfpga/theora_353x353t.tf1.7http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353t.tf?revision=1.7&view=markupMExp77*** empty log message ***2008-04-0907:37+0000jlarreyfpga/theora_353x353t.tf1.6http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353t.tf?revision=1.6&view=markupMExp7940*** empty log message ***2008-04-0907:18+0000jlarreyfpga/theora_353linear1028rgb.dat1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/linear1028rgb.dat?revision=1.1&view=markupAExp00*** empty log message ***2008-04-0711:32+0000jlarreyfpga/theora_353pxdpath.sav1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/pxdpath.sav?revision=1.1&view=markupAExp00Pixel data path simulation2008-04-0307:09+0000jlarreyfpga/theora_353compressor_one.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/compressor_one.v?revision=1.2&view=markupMExp11Back with 353 sensor{pix,trig} blocks. All memory channels have some (valid ?) output. Modified some sensors parameters for simulation.2008-04-0215:26+0000jlarreyfpga/theora_353channel0.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/channel0.v?revision=1.2&view=markupMExp52fpga/theora_353channel1.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/channel1.v?revision=1.2&view=markupMExp51fpga/theora_353ddr.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/ddr.v?revision=1.2&view=markupMExp42fpga/theora_353ioports353.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/ioports353.v?revision=1.3&view=markupMExp212fpga/theora_353mcontr_8chn.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/mcontr_8chn.v?revision=1.2&view=markupMExp167fpga/theora_353sensor12bits.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/sensor12bits.v?revision=1.3&view=markupMExp11fpga/theora_353sensorpads353.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/sensorpads353.v?revision=1.2&view=markupMExp103fpga/theora_353sensorpix353.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/sensorpix353.v?revision=1.2&view=markupMExp41103fpga/theora_353sensorpix353t.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/sensorpix353t.v?revision=1.2&view=markupMExp11fpga/theora_353x353.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353.v?revision=1.3&view=markupMExp10485fpga/theora_353x353t.tf1.5http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353t.tf?revision=1.5&view=markupMExp3518fpga/theora_353x353t_tasks.tf1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353t_tasks.tf?revision=1.4&view=markupMExp407Back with 353 sensor{pix,trig} blocks. All memory channels have some (valid ?) output. Modified some sensors parameters for simulation.2008-03-2815:27+0000jlarreyfpga/theora_353sensor12bits.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/sensor12bits.v?revision=1.2&view=markupMExp11fpga/theora_353x353t.tf1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353t.tf?revision=1.4&view=markupMExp154Modified sensor parameters to produce the same data than the 333 testbench (PXD = 0010, 0020, 0030 ...) in order to make comparisons2008-03-2616:52+0000jlarreyfpga/theora_353sensorpix353t.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/sensorpix353t.v?revision=1.1&view=markupAExp00fpga/theora_353x353.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353.v?revision=1.2&view=markupMExp8483fpga/theora_353x353t.tf1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353t.tf?revision=1.3&view=markupMExp46112fpga/theora_353x353t_parameters.tf1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353t_parameters.tf?revision=1.2&view=markupMExp11fpga/theora_353x353t_tasks.tf1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353t_tasks.tf?revision=1.3&view=markupMExp4640Updates of sensorpix and sensortrig (sensor interface)2008-03-1910:19+0000jlarreyfpga/theora_353ioports353.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/ioports353.v?revision=1.2&view=markupMExp32fpga/theora_353x353t.tf1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353t.tf?revision=1.2&view=markupMExp4640fpga/theora_353x353t_tasks.tf1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353t_tasks.tf?revision=1.2&view=markupMExp55Simulation updated (init_sdram works)2008-03-1716:05+0000jlarreyfpga/theora_353x353t.tf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353t.tf?revision=1.1&view=markupAExp00fpga/theora_353x353t_parameters.tf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353t_parameters.tf?revision=1.1&view=markupAExp00fpga/theora_353x353t_tasks.tf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353t_tasks.tf?revision=1.1&view=markupAExp00*** empty log message ***2008-03-1716:02+0000jlarreyfpga/theora_353x353_sim.sh1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353_sim.sh?revision=1.2&view=markupMExp55*** empty log message ***2008-03-1112:33+0000jlarreyfpga/theora_353xdct333.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/xdct333.v?revision=1.2&view=markupRdead00*** empty log message ***2008-03-1112:15+0000jlarreyfpga/theora_353__ISE_repository_x353t.ise_.lock1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/__ISE_repository_x353t.ise_.lock?revision=1.1&view=markupAExp00fpga/theora_353bit_packager.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/bit_packager.v?revision=1.1&view=markupAExp00fpga/theora_353camsync.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/camsync.v?revision=1.1&view=markupAExp00fpga/theora_353channel2.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/channel2.v?revision=1.1&view=markupAExp00fpga/theora_353channel3.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/channel3.v?revision=1.1&view=markupAExp00fpga/theora_353clkios353.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/clkios353.v?revision=1.1&view=markupAExp00fpga/theora_353color_proc333t.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/color_proc333t.v?revision=1.1&view=markupAExp00fpga/theora_353compressor_all.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/compressor_all.v?revision=1.1&view=markupAExp00fpga/theora_353compressor_one.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/compressor_one.v?revision=1.1&view=markupAExp00fpga/theora_353compressor_two.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/compressor_two.v?revision=1.1&view=markupAExp00fpga/theora_353csconvert333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/csconvert333.v?revision=1.1&view=markupAExp00fpga/theora_353dc_predict.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/dc_predict.v?revision=1.1&view=markupAExp00fpga/theora_353dc_predict_calc.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/dc_predict_calc.v?revision=1.1&view=markupAExp00fpga/theora_353ddr.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/ddr.v?revision=1.1&view=markupAExp00fpga/theora_353ddr_parameters.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/ddr_parameters.v?revision=1.1&view=markupAExp00fpga/theora_353dma_fifo333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/dma_fifo333.v?revision=1.1&view=markupAExp00fpga/theora_353dma_fifo353.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/dma_fifo353.v?revision=1.1&view=markupAExp00fpga/theora_353encode_dct.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/encode_dct.v?revision=1.1&view=markupAExp00fpga/theora_353encoderDCAC333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/encoderDCAC333.v?revision=1.1&view=markupAExp00fpga/theora_353extjtag.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/extjtag.v?revision=1.1&view=markupAExp00fpga/theora_353fdct_1d.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/fdct_1d.v?revision=1.1&view=markupAExp00fpga/theora_353fdct_2d.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/fdct_2d.v?revision=1.1&view=markupAExp00fpga/theora_353glbl.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/glbl.v?revision=1.1&view=markupAExp00fpga/theora_353histogram353.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/histogram353.v?revision=1.1&view=markupAExp00fpga/theora_353idct_1d.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/idct_1d.v?revision=1.1&view=markupAExp00fpga/theora_353idct_2d.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/idct_2d.v?revision=1.1&view=markupAExp00fpga/theora_353interrupts_vector333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/interrupts_vector333.v?revision=1.1&view=markupAExp00fpga/theora_353ioports353.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/ioports353.v?revision=1.1&view=markupAExp00fpga/theora_353macros353.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/macros353.v?revision=1.1&view=markupAExp00fpga/theora_353mcontr_8chn.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/mcontr_8chn.v?revision=1.1&view=markupAExp00fpga/theora_353mcontr_arbiter.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/mcontr_arbiter.v?revision=1.1&view=markupAExp00fpga/theora_353mcontr_cmd.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/mcontr_cmd.v?revision=1.1&view=markupAExp00fpga/theora_353mcontr_frame_rd.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/mcontr_frame_rd.v?revision=1.1&view=markupAExp00fpga/theora_353mcontr_frame_wr.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/mcontr_frame_wr.v?revision=1.1&view=markupAExp00fpga/theora_353mcontr_line512_rd.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/mcontr_line512_rd.v?revision=1.1&view=markupAExp00fpga/theora_353mcontr_line512_wr.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/mcontr_line512_wr.v?revision=1.1&view=markupAExp00fpga/theora_353mcontr_refresh.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/mcontr_refresh.v?revision=1.1&view=markupAExp00fpga/theora_353mcontr_tiles20x20_rd.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/mcontr_tiles20x20_rd.v?revision=1.1&view=markupAExp00fpga/theora_353mcontr_tok_rd.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/mcontr_tok_rd.v?revision=1.1&view=markupAExp00fpga/theora_353mcontr_tok_wr.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/mcontr_tok_wr.v?revision=1.1&view=markupAExp00fpga/theora_353mcontr_tokens.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/mcontr_tokens.v?revision=1.1&view=markupAExp00fpga/theora_353pack_tokens.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/pack_tokens.v?revision=1.1&view=markupAExp00fpga/theora_353qdeq.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/qdeq.v?revision=1.1&view=markupAExp00fpga/theora_353reorder_hilbert.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/reorder_hilbert.v?revision=1.1&view=markupAExp00fpga/theora_353resync_tokens_wr.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/resync_tokens_wr.v?revision=1.1&view=markupAExp00fpga/theora_353rtc353.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/rtc353.v?revision=1.1&view=markupAExp00fpga/theora_353sdram_phase.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/sdram_phase.v?revision=1.1&view=markupAExp00fpga/theora_353sdseq353.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/sdseq353.v?revision=1.1&view=markupAExp00fpga/theora_353sensdcclk333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/sensdcclk333.v?revision=1.1&view=markupAExp00fpga/theora_353sensor.dat1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/sensor.dat?revision=1.1&view=markupAExp00fpga/theora_353sensor12bits.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/sensor12bits.v?revision=1.1&view=markupAExp00fpga/theora_353sensor_phase.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/sensor_phase.v?revision=1.1&view=markupAExp00fpga/theora_353sensorpads353.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/sensorpads353.v?revision=1.1&view=markupAExp00fpga/theora_353sensorpix353.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/sensorpix353.v?revision=1.1&view=markupAExp00fpga/theora_353stuffer333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/stuffer333.v?revision=1.1&view=markupAExp00fpga/theora_353token_encode.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/token_encode.v?revision=1.1&view=markupAExp00fpga/theora_353twelve_ios.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/twelve_ios.v?revision=1.1&view=markupAExp00fpga/theora_353x353.ucf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353.ucf?revision=1.1&view=markupAExp00fpga/theora_353x353.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353.v?revision=1.1&view=markupAExp00fpga/theora_353x353_1.tf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353_1.tf?revision=1.1&view=markupAExp00fpga/theora_353x353_1.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353_1.v?revision=1.1&view=markupAExp00fpga/theora_353x353_1tasks.tf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353_1tasks.tf?revision=1.1&view=markupAExp00fpga/theora_353x353_347_1.tf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353_347_1.tf?revision=1.1&view=markupAExp00fpga/theora_353x353_347_sim.sh1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353_347_sim.sh?revision=1.1&view=markupAExp00fpga/theora_353x353_sta.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353_sta.v?revision=1.1&view=markupAExp00fpga/theora_353x353_summary.html1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353_summary.html?revision=1.1&view=markupAExp00fpga/theora_353x353t.ise_ISE_Backup1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353t.ise_ISE_Backup?revision=1.1&view=markupAExp00fpga/theora_353x353t.restore1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353t.restore?revision=1.1&view=markupAExp00fpga/theora_353xdct333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/xdct333.v?revision=1.1&view=markupAExp00*** empty log message ***2008-03-1110:57+0000jlarreyfpga/theora_353x353_import.tcl1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353_import.tcl?revision=1.1&view=markupAExp00fpga/theora_353x353_sim.sh1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353_sim.sh?revision=1.1&view=markupAExp00fpga/theora_353x353t.ise1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/x353t.ise?revision=1.1&view=markupAExp00*** empty log message ***2008-03-1110:18+0000jlarreyfpga/theora_353channel1.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/channel1.v?revision=1.1&view=markupAExp00*** empty log message ***2008-03-1110:11+0000jlarreyfpga/theora_353channel0.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora_353/channel0.v?revision=1.1&view=markupAExp00*** empty log message ***2006-06-2616:53+0000dzhimievfpga/x333_usbx333.bit1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/x333.bit?revision=1.3&view=markupMExp17011634fpga/x333_usbx333.ise1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/x333.ise?revision=1.2&view=markupMExp69209fpga/x333_usbx333.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/x333.v?revision=1.2&view=markupMExp134added timestamping2006-06-2616:29+0000dzhimievfpga/x333_usbrtc333.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/rtc333.v?revision=1.2&view=markupMExp1104*** empty log message ***2006-06-2616:23+0000dzhimievfpga/x333_usbtimestamp333a.vhd1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/timestamp333a.vhd?revision=1.1&view=markupAExp00timestamp vhdl module2006-05-0305:16+0000baton75fpga/x333_usbx333.bit1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/x333.bit?revision=1.2&view=markupMExp16261619New firmware with bugfixing.2006-05-0305:14+0000baton75fpga/x333_usbx333_2.tf1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/x333_2.tf?revision=1.2&view=markupMExp151149Add simple USB testbench.2006-05-0305:13+0000baton75fpga/x333_usbusb.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/usb.v?revision=1.2&view=markupMExp1218Bigfix ioports.2006-04-2603:18+0000spectr_rainfpga/x333_usbx333_2.tf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/x333_2.tf?revision=1.1&view=markupAExp00fork 333 jpeg code with USB core2006-04-2603:16+0000spectr_rainfpga/x333_usbx333.ise1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/x333.ise?revision=1.1&view=markupAExp00fork 333 jpeg code with USB core2006-04-2602:36+0000spectr_rainfpga/x333_usbRxFifo.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/RxFifo.v?revision=1.1&view=markupAExp00fpga/x333_usbRxFifoBI.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/RxFifoBI.v?revision=1.1&view=markupAExp00fpga/x333_usbSIETransmitter.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/SIETransmitter.v?revision=1.1&view=markupAExp00fpga/x333_usbTxFifo.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/TxFifo.v?revision=1.1&view=markupAExp00fpga/x333_usbTxFifoBI.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/TxFifoBI.v?revision=1.1&view=markupAExp00fpga/x333_usbUSBHostControlBI.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/USBHostControlBI.v?revision=1.1&view=markupAExp00fpga/x333_usbUSBSlaveControlBI.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/USBSlaveControlBI.v?revision=1.1&view=markupAExp00fpga/x333_usbclkios333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/clkios333.v?revision=1.1&view=markupAExp00fpga/x333_usbcolor_proc.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/color_proc.v?revision=1.1&view=markupAExp00fpga/x333_usbcolor_proc333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/color_proc333.v?revision=1.1&view=markupAExp00fpga/x333_usbcompressor.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/compressor.v?revision=1.1&view=markupAExp00fpga/x333_usbcompressor333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/compressor333.v?revision=1.1&view=markupAExp00fpga/x333_usbddr.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/ddr.v?revision=1.1&view=markupAExp00fpga/x333_usbddr_parameters.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/ddr_parameters.v?revision=1.1&view=markupAExp00fpga/x333_usbdescrproc333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/descrproc333.v?revision=1.1&view=markupAExp00fpga/x333_usbdirectcontrol.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/directcontrol.v?revision=1.1&view=markupAExp00fpga/x333_usbdma_cntrl.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/dma_cntrl.v?revision=1.1&view=markupAExp00fpga/x333_usbdma_cntrl333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/dma_cntrl333.v?revision=1.1&view=markupAExp00fpga/x333_usbdma_fifo333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/dma_fifo333.v?revision=1.1&view=markupAExp00fpga/x333_usbdpMem_dc.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/dpMem_dc.v?revision=1.1&view=markupAExp00fpga/x333_usbdummy_usb.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/dummy_usb.v?revision=1.1&view=markupAExp00fpga/x333_usbencoderDCAC.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/encoderDCAC.v?revision=1.1&view=markupAExp00fpga/x333_usbencoderDCAC333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/encoderDCAC333.v?revision=1.1&view=markupAExp00fpga/x333_usbendpMux.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/endpMux.v?revision=1.1&view=markupAExp00fpga/x333_usbfifoMux.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/fifoMux.v?revision=1.1&view=markupAExp00fpga/x333_usbfifoRTL.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/fifoRTL.v?revision=1.1&view=markupAExp00fpga/x333_usbgetpacket.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/getpacket.v?revision=1.1&view=markupAExp00fpga/x333_usbglbl.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/glbl.v?revision=1.1&view=markupAExp00fpga/x333_usbhctxportarbiter.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/hctxportarbiter.v?revision=1.1&view=markupAExp00fpga/x333_usbhistogram333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/histogram333.v?revision=1.1&view=markupAExp00fpga/x333_usbhostSlaveMux.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/hostSlaveMux.v?revision=1.1&view=markupAExp00fpga/x333_usbhostSlaveMuxBI.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/hostSlaveMuxBI.v?revision=1.1&view=markupAExp00fpga/x333_usbhostcontroller.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/hostcontroller.v?revision=1.1&view=markupAExp00fpga/x333_usbhuffman.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/huffman.v?revision=1.1&view=markupAExp00fpga/x333_usbhuffman333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/huffman333.v?revision=1.1&view=markupAExp00fpga/x333_usbinterrupts.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/interrupts.v?revision=1.1&view=markupAExp00fpga/x333_usbinterrupts333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/interrupts333.v?revision=1.1&view=markupAExp00fpga/x333_usbinterrupts_vector333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/interrupts_vector333.v?revision=1.1&view=markupAExp00fpga/x333_usbioports.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/ioports.v?revision=1.1&view=markupAExp00fpga/x333_usbioports323.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/ioports323.v?revision=1.1&view=markupAExp00fpga/x333_usbioports333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/ioports333.v?revision=1.1&view=markupAExp00fpga/x333_usblineControlUpdate.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/lineControlUpdate.v?revision=1.1&view=markupAExp00fpga/x333_usbmacros333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/macros333.v?revision=1.1&view=markupAExp00fpga/x333_usbmcontr.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/mcontr.v?revision=1.1&view=markupAExp00fpga/x333_usbmcontr333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/mcontr333.v?revision=1.1&view=markupAExp00fpga/x333_usbmt48lc8m16a2.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/mt48lc8m16a2.v?revision=1.1&view=markupAExp00fpga/x333_usbprocessRxBit.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/processRxBit.v?revision=1.1&view=markupAExp00fpga/x333_usbprocessRxByte.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/processRxByte.v?revision=1.1&view=markupAExp00fpga/x333_usbprocessTxByte.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/processTxByte.v?revision=1.1&view=markupAExp00fpga/x333_usbquantizator.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/quantizator.v?revision=1.1&view=markupAExp00fpga/x333_usbquantizator333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/quantizator333.v?revision=1.1&view=markupAExp00fpga/x333_usbreadUSBWireData.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/readUSBWireData.v?revision=1.1&view=markupAExp00fpga/x333_usbrtc333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/rtc333.v?revision=1.1&view=markupAExp00fpga/x333_usbrxStatusMonitor.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/rxStatusMonitor.v?revision=1.1&view=markupAExp00fpga/x333_usbsctxportarbiter.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/sctxportarbiter.v?revision=1.1&view=markupAExp00fpga/x333_usbsdram_phase.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/sdram_phase.v?revision=1.1&view=markupAExp00fpga/x333_usbsdseq333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/sdseq333.v?revision=1.1&view=markupAExp00fpga/x333_usbsendpacket.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/sendpacket.v?revision=1.1&view=markupAExp00fpga/x333_usbsendpacketarbiter.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/sendpacketarbiter.v?revision=1.1&view=markupAExp00fpga/x333_usbsendpacketcheckpreamble.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/sendpacketcheckpreamble.v?revision=1.1&view=markupAExp00fpga/x333_usbsensdcclk.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/sensdcclk.v?revision=1.1&view=markupAExp00fpga/x333_usbsensdcclk333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/sensdcclk333.v?revision=1.1&view=markupAExp00fpga/x333_usbsensorpix.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/sensorpix.v?revision=1.1&view=markupAExp00fpga/x333_usbsensorpix323.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/sensorpix323.v?revision=1.1&view=markupAExp00fpga/x333_usbsensorpix333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/sensorpix333.v?revision=1.1&view=markupAExp00fpga/x333_usbsiereceiver.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/siereceiver.v?revision=1.1&view=markupAExp00fpga/x333_usbsix_ios.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/six_ios.v?revision=1.1&view=markupAExp00fpga/x333_usbslaveDirectcontrol.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/slaveDirectcontrol.v?revision=1.1&view=markupAExp00fpga/x333_usbslaveGetpacket.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/slaveGetpacket.v?revision=1.1&view=markupAExp00fpga/x333_usbslaveRxStatusMonitor.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/slaveRxStatusMonitor.v?revision=1.1&view=markupAExp00fpga/x333_usbslaveSendpacket.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/slaveSendpacket.v?revision=1.1&view=markupAExp00fpga/x333_usbslavecontroller.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/slavecontroller.v?revision=1.1&view=markupAExp00fpga/x333_usbsofcontroller.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/sofcontroller.v?revision=1.1&view=markupAExp00fpga/x333_usbsoftransmit.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/softransmit.v?revision=1.1&view=markupAExp00fpga/x333_usbspeedCtrlMux.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/speedCtrlMux.v?revision=1.1&view=markupAExp00fpga/x333_usbstuffer.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/stuffer.v?revision=1.1&view=markupAExp00fpga/x333_usbstuffer333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/stuffer333.v?revision=1.1&view=markupAExp00fpga/x333_usbupdateCRC16.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/updateCRC16.v?revision=1.1&view=markupAExp00fpga/x333_usbupdateCRC5.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/updateCRC5.v?revision=1.1&view=markupAExp00fpga/x333_usbusb.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/usb.v?revision=1.1&view=markupAExp00fpga/x333_usbusbConstants_h.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/usbConstants_h.v?revision=1.1&view=markupAExp00fpga/x333_usbusbHostControl.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/usbHostControl.v?revision=1.1&view=markupAExp00fpga/x333_usbusbHostControl_h.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/usbHostControl_h.v?revision=1.1&view=markupAExp00fpga/x333_usbusbHostSlave.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/usbHostSlave.v?revision=1.1&view=markupAExp00fpga/x333_usbusbHostSlaveWrap.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/usbHostSlaveWrap.v?revision=1.1&view=markupAExp00fpga/x333_usbusbHostSlave_h.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/usbHostSlave_h.v?revision=1.1&view=markupAExp00fpga/x333_usbusbSerialInterfaceEngine.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/usbSerialInterfaceEngine.v?revision=1.1&view=markupAExp00fpga/x333_usbusbSerialInterfaceEngine_h.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/usbSerialInterfaceEngine_h.v?revision=1.1&view=markupAExp00fpga/x333_usbusbSlaveControl.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/usbSlaveControl.v?revision=1.1&view=markupAExp00fpga/x333_usbusbSlaveControl_h.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/usbSlaveControl_h.v?revision=1.1&view=markupAExp00fpga/x333_usbusbTxWireArbiter.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/usbTxWireArbiter.v?revision=1.1&view=markupAExp00fpga/x333_usbwishBoneBI.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/wishBoneBI.v?revision=1.1&view=markupAExp00fpga/x333_usbwishBoneBus_h.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/wishBoneBus_h.v?revision=1.1&view=markupAExp00fpga/x333_usbwriteUSBWireData.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/writeUSBWireData.v?revision=1.1&view=markupAExp00fpga/x333_usbx313.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/x313.v?revision=1.1&view=markupAExp00fpga/x333_usbx323.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/x323.v?revision=1.1&view=markupAExp00fpga/x333_usbx333.bit1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/x333.bit?revision=1.1&view=markupAExp00fpga/x333_usbx333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/x333.v?revision=1.1&view=markupAExp00fpga/x333_usbxdct.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/xdct.v?revision=1.1&view=markupAExp00fpga/x333_usbxdct333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/xdct333.v?revision=1.1&view=markupAExp00fpga/x333_usbzr32112.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/x333_usb/zr32112.v?revision=1.1&view=markupAExp00fork 333 jpeg code with USB core2005-03-1806:00+0000elphelfpga/theorax333.mrp1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.mrp?revision=1.1&view=markupAExp00fpga/theorax333.par1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.par?revision=1.1&view=markupAExp00fpga/theorax333.syr1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.syr?revision=1.1&view=markupAExp00outputs from XIlinx tools running on the design2005-03-1805:59+0000elphelfpga/theorax333.npl1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.npl?revision=1.1&view=markupAExp00project file for Xilinx ISE2005-03-1805:57+0000elphelfpga/theoracsconvert333.v1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/csconvert333.v?revision=1.4&view=markupMExp1213fpga/theoraencode_dct.v1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/encode_dct.v?revision=1.4&view=markupMExp53fpga/theoramcontr_tok_wr.v1.6http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_tok_wr.v?revision=1.6&view=markupMExp62fpga/theorax333.bit1.5http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.bit?revision=1.5&view=markupMExp14051461fpga/theorax333.v1.15http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.v?revision=1.15&view=markupMExp41fpga/theorax333t.tf1.10http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333t.tf?revision=1.10&view=markupMExp524version 03330029, fixed several bugs while running camera in different modes. Implemented overflow prevention in processing of color saturation.2005-03-1105:40+0000elphelfpga/theorabit_packager.v1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/bit_packager.v?revision=1.4&view=markupMExp2014fpga/theorax333.bit1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.bit?revision=1.4&view=markupMExp14581393fpga/theorax333.v1.14http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.v?revision=1.14&view=markupMExp52fpga/theorax333t.tf1.9http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333t.tf?revision=1.9&view=markupMExp21rev 033300262005-03-1007:01+0000elphelfpga/theorabit_packager.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/bit_packager.v?revision=1.3&view=markupMExp105fpga/theorachannel0.v1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/channel0.v?revision=1.4&view=markupMExp83fpga/theoracompressor_one.v1.8http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_one.v?revision=1.8&view=markupMExp259fpga/theoracompressor_two.v1.10http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_two.v?revision=1.10&view=markupMExp91fpga/theoradma_fifo333.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/dma_fifo333.v?revision=1.3&view=markupMExp294fpga/theoramcontr_8chn.v1.8http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_8chn.v?revision=1.8&view=markupMExp80fpga/theorareorder_hilbert.v1.6http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/reorder_hilbert.v?revision=1.6&view=markupMExp115fpga/theorax333.bit1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.bit?revision=1.3&view=markupMExp13941424fpga/theorax333.v1.13http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.v?revision=1.13&view=markupMExp183fpga/theorax333t.tf1.8http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333t.tf?revision=1.8&view=markupMExp7025fpga/theorax333t_tasks.tf1.7http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333t_tasks.tf?revision=1.7&view=markupMExp42bug fixes to rev 033300252005-03-0523:56+0000elphelfpga/theoracolor_proc333t.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/color_proc333t.v?revision=1.3&view=markupMExp3824fpga/theoracompressor_all.v1.7http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_all.v?revision=1.7&view=markupMExp10925fpga/theoracompressor_two.v1.9http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_two.v?revision=1.9&view=markupMExp4797fpga/theoracsconvert333.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/csconvert333.v?revision=1.3&view=markupMExp5413fpga/theoradc_predict.v1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/dc_predict.v?revision=1.4&view=markupMExp411fpga/theorareorder_hilbert.v1.5http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/reorder_hilbert.v?revision=1.5&view=markupMExp131fpga/theoratoken_encode.v1.5http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/token_encode.v?revision=1.5&view=markupMExp5277fpga/theorax333.bit1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.bit?revision=1.2&view=markupMExp14251427fpga/theorax333.ucf1.5http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.ucf?revision=1.5&view=markupMExp21fpga/theorax333.v1.12http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.v?revision=1.12&view=markupMExp111fpga/theorax333t.tf1.7http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333t.tf?revision=1.7&view=markupMExp5217fpga/theorax333t_tasks.tf1.6http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333t_tasks.tf?revision=1.6&view=markupMExp241Cumulative bug fixes to FPGA rev 03330021.2005-02-2321:23+0000elphelfpga/theoramcontr_tok_rd.v1.7http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_tok_rd.v?revision=1.7&view=markupMExp4426fpga/theorax333.v1.11http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.v?revision=1.11&view=markupMExp31fpga/theorax333t.tf1.6http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333t.tf?revision=1.6&view=markupMExp259bug fix in mcontr_tok_rd.v2005-02-1923:18+0000elphelfpga/theorax333.bit1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.bit?revision=1.1&view=markupAExp00FPGA image - rev 0333001b2005-02-1923:16+0000elphelfpga/theorause_huffman_table.dat1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/use_huffman_table.dat?revision=1.2&view=markupMExp42fpga/theorax333.ucf1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.ucf?revision=1.4&view=markupMExp173172fpga/theorax333.v1.10http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.v?revision=1.10&view=markupMExp62New FPGA pinout for rev B2005-01-2601:14+0000elphelfpga/theorax333t_tasks.tf1.5http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333t_tasks.tf?revision=1.5&view=markupMExp334fixed bug that prepared all quantization tables the same (it was dicovered by color blocks in the decoder output, removed some already commented out code2005-01-2601:11+0000elphelfpga/theorax333t.tf1.5http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333t.tf?revision=1.5&view=markupMExp959added more test output dump files (to compare with decoder) changed quantization values2005-01-2601:08+0000elphelfpga/theorax333.ucf1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.ucf?revision=1.3&view=markupMExp256Changed some TIG (timing ignore) constraints to double cycle ones, added more of such (acually easin constraints)2005-01-2601:05+0000elphelfpga/theorax333.v1.9http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.v?revision=1.9&view=markupMExp65Swapped output bytes, changed Rev number and copyright dates2005-01-2600:56+0000elphelfpga/theoradc_predict.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/dc_predict.v?revision=1.3&view=markupMExp91moved 2's complement -> {sign,abs} conversion on the output here from the module above2005-01-2600:52+0000elphelfpga/theoradc_predict_calc.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/dc_predict_calc.v?revision=1.2&view=markupMExp167Two bugs were discovered and fixed while testing the output data with a standard decoder, both related to replacing the predicted value with one of the 3 neighbours (L, DL, D) if they are all present2005-01-2600:47+0000elphelfpga/theoracompressor_one.v1.7http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_one.v?revision=1.7&view=markupMExp257Two bugs fixed that were discovered when feeding the output to the standard decoder. One - shift by 128 for both Y and C (on the input of forward DCT and output of the inverse DCT), the other - dc_predict was providing 2's complement output, and dct_encode expected sign+magnitude2005-01-2600:40+0000elphelfpga/theorachannel0.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/channel0.v?revision=1.3&view=markupMExp138fpga/theorachannel1.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/channel1.v?revision=1.2&view=markupMExp1310Added register level to ease timing2005-01-2208:11+0000elphelfpga/theoracompressor_two.v1.8http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_two.v?revision=1.8&view=markupMExp7324fpga/theoratoken_encode.v1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/token_encode.v?revision=1.4&view=markupMExp8110fixed some bugs while running the output data from the FPGA thropugh the actual decoder2005-01-2001:11+0000elphelfpga/theoracompressor_two.v1.7http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_two.v?revision=1.7&view=markupMExp125Made the index to Huffman group conversion match Theora codecs - there was an error in documentation2005-01-1717:50+0000elphelfpga/theorax333.v1.8http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.v?revision=1.8&view=markupMExp11497implemented debug mode (serial readout of internal data registers). Unfortunately synthesis tool gives internal errors on the attempts to directly access registers through hieararchy so all the data should be passed through the chain of modules I/Os2005-01-1717:46+0000elphelfpga/theorax333.ucf1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.ucf?revision=1.2&view=markupMExp11put TIG on data bus after making sure no module uses it first cycle of the 2-cycle window.2005-01-1717:43+0000elphelfpga/theorax333t.tf1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333t.tf?revision=1.4&view=markupMExp72fpga/theorax333t_parameters.tf1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333t_parameters.tf?revision=1.3&view=markupMExp4339fpga/theorax333t_tasks.tf1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333t_tasks.tf?revision=1.4&view=markupMExp152added support for the debug mode simulation2005-01-1717:42+0000elphelfpga/theoratoken_encode.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/token_encode.v?revision=1.3&view=markupMExp63moved table address write strobe so no data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing2005-01-1717:41+0000elphelfpga/theorasdram_phase.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/sdram_phase.v?revision=1.2&view=markupMExp628moved PIO data read strobe so no data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing2005-01-1717:40+0000elphelfpga/theoraqdeq.v1.6http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/qdeq.v?revision=1.6&view=markupMExp66moved table address write strobe so mno data will be used in the first of the 2-cycles long valid window to be able to ease data bus timing2005-01-1717:38+0000elphelfpga/theoramcontr_tok_wr.v1.5http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_tok_wr.v?revision=1.5&view=markupMExp130added debug mode2005-01-1717:36+0000elphelfpga/theoramcontr_cmd.v1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_cmd.v?revision=1.4&view=markupMExp611moved strobes that use PIO data 1 cycle behind to easy timing on data bus2005-01-1717:34+0000elphelfpga/theoramcontr_8chn.v1.7http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_8chn.v?revision=1.7&view=markupMExp237added debug mode2005-01-1717:33+0000elphelfpga/theoramacros333.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/macros333.v?revision=1.3&view=markupMExp6438added shift registers to read debug data out2005-01-1717:32+0000elphelfpga/theoraioports333t.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/ioports333t.v?revision=1.3&view=markupMExp34189added signals for debugging purposes, cleaned up some code2005-01-1717:30+0000elphelfpga/theoradefines333.vh1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/defines333.vh?revision=1.3&view=markupMExp10added debug mode2005-01-1717:29+0000elphelfpga/theoracompressor_two.v1.6http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_two.v?revision=1.6&view=markupMExp64moved table address write strobe2005-01-1717:28+0000elphelfpga/theoracompressor_all.v1.6http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_all.v?revision=1.6&view=markupMExp180added debug signals2005-01-1717:28+0000elphelfpga/theoracompressor_one.v1.6http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_one.v?revision=1.6&view=markupMExp162moved table address strobe 1 cycleadded debug signals2005-01-1717:26+0000elphelfpga/theorachannel3.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/channel3.v?revision=1.3&view=markupMExp11comments updated2005-01-1622:12+0000elphelfpga/theoradma_cntrl333.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/dma_cntrl333.v?revision=1.2&view=markupRdead00not used anymore2005-01-1620:34+0000elphelfpga/theoramcontr_8chn.v1.6http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_8chn.v?revision=1.6&view=markupMExp402fpga/theorax333.v1.7http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.v?revision=1.7&view=markupMExp63fixed bug (signal between different clock domains) and added new status bit for troubleshooting2005-01-1609:08+0000elphelfpga/theoramcontr_8chn.v1.5http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_8chn.v?revision=1.5&view=markupMExp53fpga/theorax333.v1.6http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.v?revision=1.6&view=markupMExp4644restored lost status bit that indicates that refresh is running - a way to find out that SDRAM is initialized2005-01-1608:21+0000elphelfpga/theoracompressor_two.v1.5http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_two.v?revision=1.5&view=markupMExp11simulation bug fix2005-01-1607:13+0000elphelfpga/theorax333.ucf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.ucf?revision=1.1&view=markupAExp00chip pinout on the model 333 PCB and timimng constraints2005-01-1606:47+0000elphelfpga/theorax333.v1.5http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.v?revision=1.5&view=markupMExp142new rev number, made changes needed for moving some modules to different clock phases2005-01-1606:46+0000elphelfpga/theorax333t.tf1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333t.tf?revision=1.3&view=markupMExp15042fpga/theorax333t_tasks.tf1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333t_tasks.tf?revision=1.3&view=markupMExp29653added possibility to save generated tables and data fro comparison wity the actual hardware2005-01-1606:44+0000elphelfpga/theoratoken_encode.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/token_encode.v?revision=1.2&view=markupMExp254bug fix, reduced table write data width, moved clock phase2005-01-1606:42+0000elphelfpga/theoramcontr_8chn.v1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_8chn.v?revision=1.4&view=markupMExp227changes caused by spreading modules between clock phases to reduce possible ground bounce and interference (channel 7 - read tokens from SDRAM moved)2005-01-1606:42+0000elphelfpga/theoramcontr_tok_rd.v1.6http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_tok_rd.v?revision=1.6&view=markupMExp208changes caused by spreading modules between clock phases to reduce possible ground bounce and interference2005-01-1606:40+0000elphelfpga/theoradefines333.vh1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/defines333.vh?revision=1.2&view=markupMExp10fpga/theoradma_fifo333.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/dma_fifo333.v?revision=1.2&view=markupMExp2810changes caused by spreading modules between clock phases to reduce possible ground bounce and interference2005-01-1606:39+0000elphelfpga/theoracompressor_one.v1.5http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_one.v?revision=1.5&view=markupMExp21just note in comments to verify the DCT pipe after changing clock phases2005-01-1606:39+0000elphelfpga/theoracompressor_two.v1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_two.v?revision=1.4&view=markupMExp8226changes caused by spreading modules between clock phases to reduce possible ground bounce and interference2005-01-1606:37+0000elphelfpga/theoracompressor_all.v1.5http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_all.v?revision=1.5&view=markupMExp338changes caused by spreading modules between clock phases to reduce possible ground bounce and interference2005-01-1606:35+0000elphelfpga/theorachannel2.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/channel2.v?revision=1.3&view=markupMExp147bug fix (found during hardware testing)2005-01-1020:54+0000elphelfpga/theoracsconvert333.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/csconvert333.v?revision=1.2&view=markupMExp21bug fix2005-01-0807:53+0000elphelfpga/theorareorder_hilbert.v1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/reorder_hilbert.v?revision=1.4&view=markupMExp21fixed bug found durin simulation of all the design together2005-01-0807:52+0000elphelfpga/theorapack_tokens.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/pack_tokens.v?revision=1.3&view=markupMExp146increased the delay from 64 to 65 cycles to fix the bug found during overall simulation2005-01-0807:50+0000elphelfpga/theoramcontr_tok_wr.v1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_tok_wr.v?revision=1.4&view=markupMExp52bug fixes durinmg overall simulation2005-01-0807:49+0000elphelfpga/theoramcontr_tok_rd.v1.5http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_tok_rd.v?revision=1.5&view=markupMExp216bug fix during overall simulation, added comments2005-01-0807:48+0000elphelfpga/theoramcontr_frame_wr.v1.5http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_frame_wr.v?revision=1.5&view=markupMExp11fixed misprint in comments2005-01-0807:47+0000elphelfpga/theorax333t.tf1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333t.tf?revision=1.2&view=markupMExp12211added tokens dump to files (one - before writing to SDRAM, the other - after reading back)2005-01-0807:46+0000elphelfpga/theorasensorpix333t.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/sensorpix333t.v?revision=1.2&view=markupMExp11bug fix (en_out instead of en)2005-01-0807:44+0000elphelfpga/theorax333t_tasks.tf1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333t_tasks.tf?revision=1.2&view=markupMExp52fixed simulation bug2005-01-0807:42+0000elphelfpga/theorazr32112.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/zr32112.v?revision=1.2&view=markupMExp21added scale to diagonal ramp pattern2005-01-0807:41+0000elphelfpga/theoracompressor_all.v1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_all.v?revision=1.4&view=markupMExp50fpga/theorainterrupts333t.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/interrupts333t.v?revision=1.2&view=markupMExp51fpga/theorax333.v1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.v?revision=1.4&view=markupMExp40fpga/theorax333_interface1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333_interface?revision=1.3&view=markupMExp21fpga/theorax333t_parameters.tf1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333t_parameters.tf?revision=1.2&view=markupMExp10write compressor command now cear compressor_done interrupt2005-01-0322:50+0000elphelfpga/theorazr32112.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/zr32112.v?revision=1.1&view=markupAExp00sensor model (was initially made for long obsolete Zoran sensor - then modified)2005-01-0322:49+0000elphelfpga/theoralinear256rgb.dat1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/linear256rgb.dat?revision=1.1&view=markupAExp00fpga/theoramap.dat1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/map.dat?revision=1.1&view=markupAExp00fpga/theorasensor.dat1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/sensor.dat?revision=1.1&view=markupAExp00fpga/theorause_huffman_table.dat1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/use_huffman_table.dat?revision=1.1&view=markupAExp00simulation data tables2005-01-0320:55+0000elphelfpga/theoraclkios333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/clkios333.v?revision=1.1&view=markupAExp00fpga/theoradma_cntrl333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/dma_cntrl333.v?revision=1.1&view=markupAExp00files from x333 designed earlier for JPEG version2005-01-0320:52+0000elphelfpga/theorax333t.tf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333t.tf?revision=1.1&view=markupAExp524version 03330029, fixed several bugs while running camera in different modes. Implemented overflow prevention in processing of color saturation.2005-01-0320:52+0000elphelfpga/theorax333t_parameters.tf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333t_parameters.tf?revision=1.1&view=markupAExp00fpga/theorax333t_tasks.tf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333t_tasks.tf?revision=1.1&view=markupAExp00simulation test fixture for complete x333+theora code2005-01-0320:49+0000elphelfpga/theorax333.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.v?revision=1.3&view=markupMExp456comments2005-01-0320:48+0000elphelfpga/theorax333_interface1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333_interface?revision=1.2&view=markupMExp945added text2005-01-0320:46+0000elphelfpga/theorapack_tokens.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/pack_tokens.v?revision=1.2&view=markupMExp22comments, copyright2005-01-0320:45+0000elphelfpga/theoramcontr_tok_wr.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_tok_wr.v?revision=1.3&view=markupMExp23573major changes due to new SDRAM map2005-01-0320:45+0000elphelfpga/theorareorder_hilbert.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/reorder_hilbert.v?revision=1.3&view=markupMExp7437code changes due to new SDRAM map2005-01-0320:44+0000elphelfpga/theoramcontr_tok_rd.v1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_tok_rd.v?revision=1.4&view=markupMExp276177major changes due to new SDRAM map2005-01-0320:43+0000elphelfpga/theoramcontr_tokens.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_tokens.v?revision=1.3&view=markupRdead00not part of a project - code from this file is moved to mcontr_8chn.v2005-01-0320:40+0000elphelfpga/theoramcontr_tiles20x20_rd.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_tiles20x20_rd.v?revision=1.3&view=markupMExp11comments2005-01-0320:37+0000elphelfpga/theoramcontr_line512_rd.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_line512_rd.v?revision=1.3&view=markupMExp11fpga/theoramcontr_line512_wr.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_line512_wr.v?revision=1.2&view=markupMExp55comments2005-01-0320:30+0000elphelfpga/theoramcontr_frame_wr.v1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_frame_wr.v?revision=1.4&view=markupMExp32bug fix2005-01-0320:29+0000elphelfpga/theoramcontr_cmd.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_cmd.v?revision=1.3&view=markupMExp33misprint fixed, updated copyright2005-01-0320:27+0000elphelfpga/theoramcontr_8chn.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_8chn.v?revision=1.3&view=markupMExp106comments, changed signal2005-01-0320:26+0000elphelfpga/theoraddr.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/ddr.v?revision=1.2&view=markupMExp40added sme debug output2005-01-0320:25+0000elphelfpga/theoracompressor_two.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_two.v?revision=1.3&view=markupMExp33comments2005-01-0320:16+0000elphelfpga/theoracompressor_one.v1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_one.v?revision=1.4&view=markupMExp76updated comments2005-01-0320:11+0000elphelfpga/theoracompressor_all.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_all.v?revision=1.3&view=markupMExp181bug fix2005-01-0320:09+0000elphelfpga/theoracolor_proc333t.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/color_proc333t.v?revision=1.2&view=markupMExp185bug fix2005-01-0320:07+0000elphelfpga/theorachannel3.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/channel3.v?revision=1.2&view=markupMExp2626fixed misprint, updated copyright2005-01-0320:05+0000elphelfpga/theorachannel0.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/channel0.v?revision=1.2&view=markupMExp2423fixed misprint, updated copyright2004-12-2123:41+0000elphelfpga/theoracompressor_all.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_all.v?revision=1.2&view=markupMExp44updated comments about table access register map2004-12-2123:40+0000elphelfpga/theoraioports333t.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/ioports333t.v?revision=1.2&view=markupMExp1010removed unused outputs from sysinterface module2004-12-2123:39+0000elphelfpga/theorax333.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.v?revision=1.2&view=markupMExp3225minor cleanup and update2004-12-2123:37+0000elphelfpga/theorax333_interface1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333_interface?revision=1.1&view=markupAExp00initial release - x333 FPGA interface description2004-12-2008:50+0000elphelfpga/theorareorder_hilbert.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/reorder_hilbert.v?revision=1.2&view=markupMExp381Replaced primitive that does not exist in Spartan 3 with the generic model2004-12-2008:48+0000elphelfpga/theoraqdeq.v1.5http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/qdeq.v?revision=1.5&view=markupMExp260reduced the table memory input width to resolve conflict with embedded multipliers2004-12-2008:44+0000elphelfpga/theoramcontr_tok_rd.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_tok_rd.v?revision=1.3&view=markupMExp913fixed dqs_re timing2004-12-2008:43+0000elphelfpga/theoramcontr_tokens.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_tokens.v?revision=1.2&view=markupMExp22fixed syntax error2004-12-2008:42+0000elphelfpga/theoramcontr_tiles20x20_rd.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_tiles20x20_rd.v?revision=1.2&view=markupMExp63Implemented clock phase control in the header file, fixed dqs_re timing2004-12-2008:41+0000elphelfpga/theoramcontr_line512_rd.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_line512_rd.v?revision=1.2&view=markupMExp53Implemented clock phase control in the header file, fixed dqs_re timing2004-12-2008:39+0000elphelfpga/theoramcontr_frame_rd.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_frame_rd.v?revision=1.3&view=markupMExp209Implemented clock phase control in the header file2004-12-2008:39+0000elphelfpga/theoramcontr_frame_wr.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_frame_wr.v?revision=1.3&view=markupMExp226Implemented clock phase control in the header file, added output2004-12-2008:38+0000elphelfpga/theoramcontr_cmd.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_cmd.v?revision=1.2&view=markupMExp10added missing register declaration2004-12-2008:37+0000elphelfpga/theoramcontr_8chn.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_8chn.v?revision=1.2&view=markupMExp214provided additional outputs, fixed dqs_re timing2004-12-2008:34+0000elphelfpga/theoramacros333.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/macros333.v?revision=1.2&view=markupMExp292Replaced library element nonexestent in Spartan3 with generic behavioral module2004-12-2008:32+0000elphelfpga/theorafdct_1d.v1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/fdct_1d.v?revision=1.4&view=markupMExp11comment syntax error2004-12-2008:30+0000elphelfpga/theorax333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/x333.v?revision=1.1&view=markupAExp62New FPGA pinout for rev B2004-12-2008:29+0000elphelfpga/theoracompressor_all.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_all.v?revision=1.1&view=markupAExp00initial release, module combining all the Theora encoding2004-12-2008:28+0000elphelfpga/theoracolor_proc333t.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/color_proc333t.v?revision=1.1&view=markupAExp00fpga/theoracsconvert333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/csconvert333.v?revision=1.1&view=markupAExp00fpga/theoradefines333.vh1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/defines333.vh?revision=1.1&view=markupAExp00fpga/theoradma_fifo333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/dma_fifo333.v?revision=1.1&view=markupAExp00fpga/theorainterrupts333t.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/interrupts333t.v?revision=1.1&view=markupAExp00fpga/theoraioports333t.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/ioports333t.v?revision=1.1&view=markupAExp00fpga/theorasdram_phase.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/sdram_phase.v?revision=1.1&view=markupAExp00fpga/theorasensdcclk333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/sensdcclk333.v?revision=1.1&view=markupAExp00fpga/theorasensorpix333t.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/sensorpix333t.v?revision=1.1&view=markupAExp00Initial release of the files, modified from original version for 313/333 cameras working in JPEG mode2004-12-2008:22+0000elphelfpga/theoracompressor_two.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_two.v?revision=1.2&view=markupMExp52provided "done" output2004-12-2008:21+0000elphelfpga/theoracompressor_one.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_one.v?revision=1.3&view=markupMExp11412Implemented clock phase control in the header file, reduced block RAM width to 18 (from 36) to resolve conflicts with embedded multipliers2004-12-2008:18+0000elphelfpga/theorachannel2.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/channel2.v?revision=1.2&view=markupMExp166Implemented clock phase control in the header file2004-12-2008:16+0000elphelfpga/theorabit_packager.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/bit_packager.v?revision=1.2&view=markupMExp61added "done" output2004-11-3002:48+0000elphelfpga/theoracompressor_two.tf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_two.tf?revision=1.1&view=markupAExp00fpga/theorahufftab80.dat1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/hufftab80.dat?revision=1.1&view=markupAExp00fpga/theoratokens12_1st.dat1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/tokens12_1st.dat?revision=1.1&view=markupAExp00test fixture and data files for simulating compressor_two2004-11-3002:47+0000elphelfpga/theorabit_packager.tf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/bit_packager.tf?revision=1.1&view=markupAExp00test fixture for bit_packager.v2004-11-3002:47+0000elphelfpga/theorabit_packager.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/bit_packager.v?revision=1.1&view=markupAExp00initial release of compressor_two that gets 12-bit "pore-tokens" from the frame memory in coded order, encodes them using Huffman tables and prepares for DMA output2004-11-3002:47+0000elphelfpga/theoracompressor_two.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_two.v?revision=1.1&view=markupAExp91bug fixes to rev 033300252004-11-3002:47+0000elphelfpga/theoratoken_encode.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/token_encode.v?revision=1.1&view=markupAExp00initial release of compressor_two that gets 12-bit "pore-tokens" from the frame memory in coded order, encodes them using Huffman tables and prepares for DMA output2004-11-3002:45+0000elphelfpga/theoraacdcscale.dat1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/acdcscale.dat?revision=1.1&view=markupAExp00fpga/theorabms.dat1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/bms.dat?revision=1.1&view=markupAExp00data files for simulatin compressor_one2004-11-3002:44+0000elphelfpga/theoramacros333.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/macros333.v?revision=1.1&view=markupAExp00several small universal modules2004-11-3002:42+0000elphelfpga/theoramcontr_tok_rd.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_tok_rd.v?revision=1.2&view=markupMExp11removed obsolete comment2004-11-1908:06+0000elphelfpga/theoracompressor_one.tf1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_one.tf?revision=1.2&view=markupMExp17699modified to match new compressor_one.v2004-11-1908:05+0000elphelfpga/theoracompressor_one.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_one.v?revision=1.2&view=markupMExp11824included map table that stores 2 bits per 2x2 macroblocks (32x32 pixels) - skip (not code) and quality - one of two alternative table sets available in the same frame.2004-11-1908:03+0000elphelfpga/theoraqdeq.v1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/qdeq.v?revision=1.4&view=markupMExp75Added more bits to the table address to be able to put more table in the same address space2004-11-1819:14+0000elphelfpga/theoraqdeq.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/qdeq.v?revision=1.3&view=markupMExp11error in comment fixed2004-11-1819:13+0000elphelfpga/theoramcontr_frame_rd.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_frame_rd.v?revision=1.2&view=markupMExp24fpga/theoramcontr_frame_wr.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_frame_wr.v?revision=1.2&view=markupMExp11copyright update, comments clean up2004-11-1819:12+0000elphelfpga/theoraidct_2d.v1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/idct_2d.v?revision=1.4&view=markupMExp83bug fix, and addition of the pre2_fo output (2 cycles ahead of the data out)2004-11-1819:10+0000elphelfpga/theorafdct_2d.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/fdct_2d.v?revision=1.3&view=markupMExp22some commented out lines removed2004-11-1819:09+0000elphelfpga/theoraencode_dct.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/encode_dct.v?revision=1.3&view=markupMExp31Minor bug fix (bug revealed itself during synthesis)2004-11-1819:07+0000elphelfpga/theoradc_predict.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/dc_predict.v?revision=1.2&view=markupMExp01comment error fixed2004-11-1819:06+0000elphelfpga/theoracompressor_one.tf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_one.tf?revision=1.1&view=markupAExp00Test fixture for compressor_one.v2004-11-1819:06+0000elphelfpga/theoracompressor_one.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/compressor_one.v?revision=1.1&view=markupAExp00Initial release of the module that combines DCT, quantizer, dequantizer, IDCT, reference frame bypass and adder/subtracter, "pre-token" encoder.2004-11-1819:04+0000elphelfpga/theorablock8x8.dat1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/block8x8.dat?revision=1.1&view=markupAExp00test data for simulation2004-11-1609:45+0000elphelfpga/theoradc_predict.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/dc_predict.v?revision=1.1&view=markupAExp00fpga/theoradc_predict_calc.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/dc_predict_calc.v?revision=1.1&view=markupAExp00Initial release of the DC predictor module2004-11-1609:43+0000elphelfpga/theoratest_encode_dct.tf1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/test_encode_dct.tf?revision=1.2&view=markupMExp109modified to support simulating of the non-coded blocks2004-11-1609:42+0000elphelfpga/theoraqdeq.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/qdeq.v?revision=1.2&view=markupMExp2316added processing of non-coded blocks2004-11-1609:40+0000elphelfpga/theoramcontr_tok_wr.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/mcontr_tok_wr.v?revision=1.2&view=markupMExp33fixed some comments, changed copyright2004-11-1609:38+0000elphelfpga/theorafdct_1d.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/fdct_1d.v?revision=1.3&view=markupMExp3320fpga/theorafdct_2d.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/fdct_2d.v?revision=1.2&view=markupMExp246fpga/theoraidct_1d.v1.4http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/idct_1d.v?revision=1.4&view=markupMExp2011fpga/theoraidct_2d.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/idct_2d.v?revision=1.3&view=markupMExp3325Added "skip" input for uncoded blocks. When active it preserves timing (and provides output synchronization) but reduces power consumption by not running most of the registers and counters.2004-11-1609:36+0000elphelfpga/theoradct_quant.tf1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/dct_quant.tf?revision=1.2&view=markupMExp241120added more modules to simulate together2004-11-1609:35+0000elphelfpga/theoraencode_dct.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/encode_dct.v?revision=1.2&view=markupMExp2322added processing of the non-coded blocks (input data is 11'h400)2004-11-0804:35+0000elphelfpga/theoradct_quant.tf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/dct_quant.tf?revision=1.1&view=markupAExp00fpga/theoraqdeq.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/qdeq.v?revision=1.1&view=markupAExp00initial release of quantizer/dequantizer2004-11-0405:44+0000elphelfpga/theoraidct.tf1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/idct.tf?revision=1.2&view=markupMExp141added synchronization requirements/means of the input data2004-11-0405:43+0000elphelfpga/theoraidct_2d.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/idct_2d.v?revision=1.2&view=markupMExp3444cleaned up, added resource usage statistics2004-11-0405:41+0000elphelfpga/theorafdct_1d.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/fdct_1d.v?revision=1.2&view=markupMExp90note about synchronization of the input data2004-11-0405:40+0000elphelfpga/theorafdct.tf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/fdct.tf?revision=1.1&view=markupAExp00fpga/theorafdct_2d.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/fdct_2d.v?revision=1.1&view=markupAExp00original release2004-11-0106:13+0000elphelfpga/theorafdct_1d.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/fdct_1d.v?revision=1.1&view=markupAExp00First version of forward DCT following algorithm suggested in Theora specs.2004-11-0106:12+0000elphelfpga/theoraidct_1d.v1.3http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/idct_1d.v?revision=1.3&view=markupMExp1313changed copyright, renamed variables2004-10-2906:53+0000elphelfpga/theoraidct.tf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/idct.tf?revision=1.1&view=markupAExp00Initial rev. of 2-D inverse DCT2004-10-2906:53+0000elphelfpga/theoraidct_1d.v1.2http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/idct_1d.v?revision=1.2&view=markupMExp9797Fixed some bugs during simulation2004-10-2906:53+0000elphelfpga/theoraidct_2d.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/idct_2d.v?revision=1.1&view=markupAExp00Initial rev. of 2-D inverse DCT2004-10-2707:21+0000elphelfpga/theoraidct_1d.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/idct_1d.v?revision=1.1&view=markupAExp00First version of 1d idct designed to Theora specs. Uses 1 multiplier and 250 slices, can run at 13 ns/pixel (6.5ns/clock_period) that should be twice the pixel rate.2004-10-2005:46+0000elphelfpga/theoraencode_dct.v1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/encode_dct.v?revision=1.1&view=markupAExp00fpga/theoratest_encode_dct.tf1.1http://elphel.cvs.sourceforge.net/viewvc/elphel/fpga/theora/test_encode_dct.tf?revision=1.1&view=markupAExp00initial version